Step 4: Check for Design Errors¶

Let's check for errors that will affect the manufacturability of your chip using Design Rule Checking (DRC).

Run a DRC check¶

In the GF+ tab, open the sample_drc_errors GDS file from project components. In the top right bar of the GDS View tab, click on the DRC button. Wait for the checking process to finish.

When the process is finished, select the DRC tab in the left navigation bar of VSCode. In this tab, errors can be reviewed. You should see a number of errors, including min_space errors. This means there isn't enough space between two polygons according to the design rules of the PDK.

Click on any DRC error to highlight it in the layout view.

Fix the errors (optional)¶

Modify the Python code to remove the errors. You can access the component from the GF+ tab and edit the code. Then run the DRC again on the GDS file and repeat until you have fixed all the DRC errors.

After fixing the errors, everything is now complete. Your chip is ready for fabrication! 🎉

Try other checks (optional)¶

Just as you checked for DRC errors, you can also check for connectivity and LVS (Layout Versus Schematic) errors using the Check Connectivity and Check LVS dropdown options under the checkmark menu in the top right.

The errors will display in the same DRC Results tab in the left sidebar of VSCode, under separate tabs for each check type Connectivity Results and LVS Results.

Next Steps¶

🎉 Congratulations! You have completed the GDSFactory+ Quickstart Guide. You have created cells, designed a circuit, simulated it, and checked for errors.

To continue your journey with GDSFactory+, proceed check out how to start a new project with PDKs and project templates in PDKs and Project Templates.

Happy building! 🏗️